| Συγγραφείς: | Kalligeros E., Kaseridis D., Kavousianos X., Nikolos D. |
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| Τίτλος: | "Reseeding-based Test Set Embedding with Reduced Test Sequences" |
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| Συνέδριο: | International Symposium on Quality Electronic Design (ISQED) |
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| Editors: | |
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| Ed: | Όχι |
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| Eds: | Όχι |
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| Σελίδες: | 226-231 |
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| Να εμφανιστεί: | Όχι |
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| Μήνας: | Μάρτιος |
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| Έτος: | 2005 |
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| Τόπος: | |
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| Εκδότης: | |
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| Δεσμός: | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1410588 |
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| Όνομα αρχείου: | |
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| Περίληψη: | A novel technique for reducing the test sequences of reseeding-based schemes is presented in this paper. The proposed
technique is generic and can be applied to test set embedding
or mixed-mode schemes based on various TPGs. The
imposed hardware overhead is very small since it is confined
to just one extra bit per seed plus one very small counter in
the scheme's control logic, while the test-sequence-length
reductions achieved are up to 44.71%. Along with the test-sequence-reduction technique, an efficient seed-selection
algorithm for the test-per-clock, LFSR-based, test set embedding
case is presented. The proposed algorithm targets the
minimization of the selected seed volumes and, combined
with the test-sequence-reduction technique, delivers results
with fewer seeds and much smaller test sequences than the
already proposed approaches. |
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English