| Abstract: | In this paper a novel reseeding architecture for scan-based BIST,
which uses an LFSR as TPG, is proposed. Multiple cells of the
LFSR are utilized as sources for feeding the scan chain in
different test phases. The LFSR generates the same state sequence
in all phases, keeping that way the implementation cost low. Also,
a dynamic reseeding scheme is adopted for further reducing the
required hardware overhead. A seed-selection algorithm is
moreover presented that, taking advantage of the multi-phase
architecture, manages to reduce the number of the required seeds
for achieving complete (100 %) fault coverage. Experimental
results demonstrate the superiority of the proposed LFSR
reseeding approach over the already known reseeding techniques. |
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