| Authors: | Gekas G., Nikolos D., Kalligeros E., Kavousianos X. |
|---|
| Title: | "Power Aware Test-Data Compression for Scan-based Testing" |
|---|
| Conference: | IEEE International Conference on Electronics, Circuits and Systems (ICECS) |
|---|
| Editors: | |
|---|
| Ed: | No |
|---|
| Eds: | No |
|---|
| Pages: | |
|---|
| To appear: | No |
|---|
| Month: | December |
|---|
| Year: | 2005 |
|---|
| Place: | |
|---|
| Pubisher: | |
|---|
| Link: | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4633432 |
|---|
| File name: | |
|---|
| Abstract: | In this paper a new approach that targets the reduction of
both the test-data volume and the scan power during the
testing of a core is proposed. For achieving the two aforementioned
goals, a novel algorithm that inserts some inverters
in the scan chain(s) of the core under test (CUT) is
presented. The proposed algorithm targets the maximization
of run-lengths of zeros (or ones) in the test set accompanying
the CUT, while imposing no performance or
area penalty since the negated outputs of the scan flip-flops
can be used for performing the necessary inversions.
This algorithm combined with the Minimum Transition
Count mapping of don't cares in a test set, as well as with
the alternating run-length code that have been recently
proposed, achieves better test-data compression and reduced
scan-power results than the relative works in the
literature. |
|---|
Greek