| Συγγραφείς: | Haniotakis T., Kalligeros E., Nikolos D., Sidiropoulos G., Tsiatouhas Y., Vergos H. |
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| Τίτλος: | "A Class of Easily Path Delay Fault Testable Circuits" |
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| Συνέδριο: | Southwest Symposium on Mixed-Signal Design (SSMSD) |
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| Editors: | |
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| Ed: | Όχι |
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| Eds: | Όχι |
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| Σελίδες: | 165-170 |
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| Να εμφανιστεί: | Όχι |
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| Μήνας: | Φεβρουάριος |
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| Έτος: | 2000 |
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| Τόπος: | |
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| Εκδότης: | |
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| Δεσμός: | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=836466 |
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| Όνομα αρχείου: | |
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| Περίληψη: | The number of physical paths in a carry save or
modified Booth multiplier, as well as in a non restoring
cellular array divider is prohibitively large for testing all
paths for delay faults. Besides, neither all paths are
robustly testable nor a basis consisting of SPP-HFRT
paths exists.
In this paper we present sufficient modifications of
the above mentioned circuits so that a basis consisting of
SPP-HFRT paths to exist, The cardinality of the derived
basis is very small. Also, hardware and delay overheads
due to the modifications are respectively small and
negligible. |
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English