| Authors: | Bakalis D., Kalligeros E., Nikolos D., Vergos H., Alexiou G. |
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| Title: | "Low Power BIST for Wallace Tree-based Fast Multipliers" |
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| Conference: | IEEE International Symposium on Quality Electronic Design (ISQED) |
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| Ed: | No |
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| Eds: | No |
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| Pages: | 433-438 |
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| To appear: | No |
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| Month: | March |
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| Year: | 2000 |
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| Place: | |
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| Pubisher: | |
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| Link: | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=838914 |
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| Abstract: | The low power as a feature of a BIST scheme is a
significant target due to quality as well as cost related
issues. In this paper we examine the testability of
multipliers based on Booth encoding and Wallace tree
summation of the partial products and we present a
methodology for deriving a low power Built In Self Test
(BIST) scheme for them. We propose several design rules
for designing the Wallace tree in order to be fully testable
under the cell fault model. The proposed low power BIST
scheme for the derived multipliers is achieved by: (a) introducing suitable Test Pattern Generators (TPG),
(b) properly assigning the TPG outputs to the multiplier
inputs and (c) significantly reducing the test set length
with respect to earlier schemes. Our results indicate that
the total power dissipated during test can be reduced
from 64.8% to 72.8%, while the average power per test
vector can be reduced from 19.6% to 27.4% and the peak
power dissipation can be reduced from 16.8% to 36.0%,
depending on the implementation of the basic cells and
the size of the multiplier. The test application time is also
significantly reduced, while the introduced BIST scheme
implementation area is small. |
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