| Περίληψη: | On-chip interconnection networks simplify the increasingly challenging process of integrating multiple functional
modules in modern Systems-on-Chip (SoCs). The routers are the
heart and backbone of such networks, and their implementation
cost (area/power) determines the cost of the whole network.
In this paper, we explore the time-multiplexing of a router’s
output ports via a folded datapath and control, where only
a portion of the router’s arbiters and crossbar multiplexers
are implemented, as a means to reduce the cost of the router
without sacrificing performance. In parallel, we propose the
incorporation of the switch-folded routers into a new form
of heterogeneous network topologies, comprising both folded
(time-multiplexed) and unfolded (conventional) routers, which
leads to effectively the same network performance, but at lower
area/energy, as compared to topologies composed entirely of full-
fledged wormhole or virtual-channel-based router designs. |
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English