| Authors: | Kalligeros E., Vergos H., Nikolos D., Tsiatouhas Y., Haniotakis T. |
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| Title: | "Path Delay Fault Testable Modified Booth Multipliers" |
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| Conference: | Design of Circuits and Integrated Systems Conference (DCIS) |
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| Editors: | |
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| Ed: | No |
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| Eds: | No |
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| Pages: | 301-306 |
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| To appear: | No |
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| Month: | November |
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| Year: | 1999 |
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| Place: | |
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| Pubisher: | |
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| Link: | |
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| File name: | 1999_DCIS.pdf##^^&&572986124.pdf |
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| Abstract: | Testing of Modified Booth Multipliers (MBMs) with
respect to path delay faults, is studied in this paper.
Design modifications are proposed and a path
selection method is suggested. The selected paths
are Single Path Propagating – Hazard Free Robustly
Testable (SPP-HFRT) and based on their delays the
delay along any other path of the MBM can be
calculated. The number of the selected paths is
impressively small compared to all paths of the
multiplier. The delay and hardware overhead
imposed by the modifications are respectively
negligible and small. |
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Greek